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| ispLSI 2064/A In-System Programmable High Density PLD Features * ENHANCEMENTS -- ispLSI 2064A is Fully Form and Function Compatible to the ispLSI 2064, with Identical Timing Specifcations and Packaging -- ispLSI 2064A is Built on an Advanced 0.35 Micron E2CMOS(R) Technology Output Routing Pool (ORP) Input Bus (R) Functional Block Diagram Output Routing Pool (ORP) B7 B6 B5 B4 -- 2000 PLD Gates -- 64 I/O Pins, Four Dedicated Inputs -- 64 Registers -- High Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 125 MHz Maximum Operating Frequency -- tpd = 7.5 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture -- Unused Product Term Shutdown Saves Power * IN-SYSTEM PROGRAMMABLE -- In-System Programmable (ISPTM) 5V Only -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control to Minimize Switching Noise -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms Input Bus A2 GLB Logic Array DQ DQ B1 DQ A3 A4 A5 A6 A7 B0 Output Routing Pool (ORP) Input Bus Fu Description 0139Bisp/2064 The ispLSI 2064 and 2064A are High Density Programmable Logic Devices. The devices contain 64 Registers, 64 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The 2064 and 2064A feature 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2064 and 2064A offer non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems. The basic unit of logic on these devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (Figure 1). There are a total of 16 GLBs in the ispLSI 2064 and 2064A devices. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com April 2000 2064_07 1 Input Bus A1 DQ B2 Output Routing Pool (ORP) * HIGH DENSITY PROGRAMMABLE LOGIC A0 Global Routing Pool (GRP) B3 Specifications ispLSI 2064/A Functional Block Diagram Figure 1. ispLSI 2064/A Functional Block Diagram GOE 0 GOE 1 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 Input Bus Generic Logic Blocks (GLBs) Megablock B7 Output Routing Pool (ORP) B6 B5 B4 Output Routing Pool (ORP) I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1 Input Bus Input Bus I/O 4 I/O 5 I/O 6 I/O 7 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 I/O 47 A0 B3 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 SCLK/IN 3 SDO/IN 2 A1 Global Routing Pool (GRP) B2 A2 B1 A3 B0 A4 A5 A6 A7 ispEN Input Bus I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 The devices also have 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by two ORPs. Each ispLSI 2064 and 2064A device contains two Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2064 and 2064A devices are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. 2 Y0 Y1 Y2 CLK 0 CLK 1 CLK 2 0139B(1)isp/2064 RESET Output Routing Pool (ORP) Specifications ispLSI 2064/A Absolute Maximum Ratings 1 Supply Voltage Vcc ................................................... -0.5 to +7.0V Input Voltage Applied .............................. -2.5 to VCC +1.0V Off-State Output Voltage Applied ........... -2.5 to VCC +1.0V Storage Temperature ..................................... -65 to 150C Case Temp. with Power Applied .................... -55 to 125C Max. Junction Temp. (TJ) with Power Applied ............ 150C 1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial TA = 0C to + 70C TA = -40C to + 85C MIN. 4.75 4.5 0 2.0 MAX. 5.25 5.5 0.8 Vcc+1 UNITS V V V V Table 2 - 0005/2064 VCC VIL VIH Capacitance (TA=25C, f=1.0 MHz) SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock Capacitance TYPICAL 8 9 15 UNITS pf pf pf TEST CONDITIONS VCC = 5.0V, VIN = 2.0V VCC = 5.0V, VI/O = 2.0V VCC = 5.0V, VY = 2.0V Table 2-0006/2064 C1 C2 C3 Data Retention Specifications PARAMETER Data Retention Erase/Reprogram Cycles MINIMUM 20 10000 MAXIMUM - - UNITS Years Cycles Table 2-0008/2064 3 Specifications ispLSI 2064/A Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V -125 Others 1.5V 1.5V See Figure 2 Table 2-0003/2064 Figure 2. Test Load + 5V R1 Device Output R2 C L* Test Point 2 ns 3 ns Output Load Conditions (see Figure 2) TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF *CL includes Test Fixture and Probe Capacitance. C Table 2-0004/2064 DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current ispEN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) 3.5V VIN VCC 0V VIN VIL 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fCLOCK = 1 MHz Commercial Industrial CONDITION MIN. - 2.4 - - - - - - - TYP. - - - - - - - 95 95 3 MAX. UNITS 0.4 - -10 10 -150 -150 -200 175 - V V A A A A mA mA mA VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4 Table 2-0007/2064 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC . 4 Specifications ispLSI 2064/A External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST #2 COND. A A A - - - A - - - - A - B C B C - - 1 2 3 4 5 6 7 8 9 4 DESCRIPTION 1 Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock 3 1 -125 - - 125 100 125 5.0 - 0.0 6.0 - 0.0 - 5.0 - - - - 4.0 4.0 7.5 10.0 - - - - 4.0 - - 4.5 - 10.0 - 12.0 12.0 7.0 7.0 - - - - -100 10.0 13.0 - - - - 5.0 - - 6.0 - 13.5 - 15.0 15.0 9.0 9.0 - - - - -80 15.0 18.5 - - - - 6.5 - - 8.0 - 17.0 - 18.0 18.0 12.0 12.0 - - MIN. MAX. MIN. MAX. MIN. MAX. UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl 1. 2. 3. 4. 100 77.0 111 6.5 - 0.0 8.0 - 0.0 - 6.5 - - - - 4.5 4.5 81.0 57.0 100 9.0 - 0.0 11.0 - 0.0 - 10.0 - - - - 5.0 5.0 Clock Frequency with External Feedback ( tsu2 + tco1) 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Product Term OE, Enable 15 Product Term OE, Disable 16 Global OE, Enable 17 Global OE, Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. Table 2 - 0030B/2064-130 5 Specifications ispLSI 2064/A Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER # 2 DESCRIPTION -125 -100 -80 UNITS MIN. MAX. MIN. MAX. MIN. MAX. Inputs tio tdin GRP tgrp GLB t4ptbp t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck ORP torp 20 21 Input Buffer Delay Dedicated Input Delay - - 0.2 1.5 - - 0.5 2.2 - - 1.8 4.4 ns ns 22 GRP Delay - 1.3 - 1.7 - 2.6 ns 23 24 25 26 27 28 29 30 31 32 33 34 35 4 Product Term Bypass Comb. Path Delay 4 Product Term Bypass Reg. Path Delay 1 Product Term/XOR Path Delay 20 Product Term/XOR Path Delay XOR Adjacent Path Delay3 - - - - - - 0.8 3.0 - - - - 3.3 4.5 5.0 5.7 6.0 6.5 0.5 - - 0.2 1.1 4.8 7.3 5.6 - - - - - - 1.2 4.0 - - - - 4.1 5.8 5.8 6.8 7.3 8.0 0.5 - - 0.3 1.3 6.1 8.6 7.1 - - - - - - 1.4 6.0 - - - - 5.6 8.1 6.8 8.0 8.8 9.8 1.3 - - 0.4 1.6 8.6 9.0 10.2 ns ns ns ns ns ns ns ns ns ns ns ns ns GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay 36 ORP Delay ORP Bypass Delay - - 0.8 0.3 - - 1.4 0.4 - - 2.0 0.5 ns ns 37 torpbp Outputs 38 tob 39 tsl 40 toen 41 todis 42 tgoe Clocks tgy0 43 tgy1/2 44 Global Reset 45 tgr Output Buffer Delay Output Slew Limited Delay Adder I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled Global Output Enable - - - - - 1.2 10.0 3.2 3.2 3.8 - - - - - 1.6 10.0 4.2 4.2 4.8 - - - - - 2.0 10.0 4.6 4.6 7.4 ns ns ns ns ns Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.3 2.3 2.3 2.3 2.7 2.7 2.7 2.7 3.6 3.6 3.6 3.6 ns ns Global Reset to GLB - 6.9 - 9.2 - 11.4 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2- 0036C/2064-130 6 Specifications ispLSI 2064/A ispLSI 2064/A Timing Model I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GRP #22 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 Reset #45 D RST #29, 30, 31, 32 GLB Reg Bypass #28 GLB Reg Delay Q ORP Bypass #37 ORP Delay #36 #38, 39 I/O Pin (Output) GLB ORP I/O Cell #21 I/O Delay #20 I/O Pin (Input) Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0,1 #43, 44 #42 #40, 41 0491/2064 Derivations of tsu, th and tco from the Product Term Clock 1 tsu = = = 3.5 ns = = = = 2.6 ns = = = = 9.4 ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2) Table 2- 0042A-2064 th tco Note: Calculations are based upon timing specifications for the ispLSI 2064/A-125L. 7 Specifications ispLSI 2064/A Power Consumption Power consumption in the ispLSI 2064 and 2064A devices depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax 160 150 140 130 120 used. Figure 4 shows the relationship between power and operating speed. ispLSI 2064/A ICC (mA) 110 100 90 80 70 1 20 40 60 80 100 120 140 fmax (MHz) Notes: Configuration of Four 16-bit Counters Typical Current at 5V, 25 C ICC can be estimated for the ispLSI 2064/A using the following equation: ICC(mA) = 38 + (# of PTs * 0.33) + (# of nets * Max freq * 0.007) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127A/2064A 8 Specifications ispLSI 2064/A Pin Description NAME I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 GOE 0, GOE 1 Y0, Y1, Y2 RESET ispEN PLCC PIN NUMBERS 26, 30, 34, 38, 45, 49, 53, 57, 68, 72, 76, 80, 3, 7, 11, 15, 67, 20, 24 23 27, 31, 35, 39, 46, 50, 54, 58, 69, 73, 77, 81, 4, 8, 12, 16, 84 66, 63 28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 5, 9, 13, 17, 29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 6, 10, 14, 18 DESCRIPTION Input/Output Pins -- These are the general purpose I/O pins used by the logic array. Global Output Enable input pins. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs in the device. Active Low (0) Reset pin which resets all registers in the device. Input -- Dedicated in-system programming enable pin. This pin is brought low to enable the programming mode. When low, the MODE, SDI, SDO and SCLK controls become active. Input -- This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the ISP state machine. When ispEN is high, it functions as a dedicated pin input. Input -- This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the ISP state machine. When ispEN is high, it functions as a dedicated input pin. Output/Input -- This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated input pin. SDI/ IN 02 25 MODE/ IN 12 42 SDO/IN 22 44 SCLK/IN 32 61 GND VCC NC1 1, 21, 2, 22, 65 19, 43, 62 64 Ground (GND) Vcc No Connect Table 2-0002A-08isp/2064 1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. 9 Specifications ispLSI 2064/A Pin Description NAME I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 GOE 0, GOE 1 Y0, Y1, Y2 RESET ispEN TQFP PIN NUMBERS 17, 21, 29, 33, 40, 44, 48, 56, 67, 71, 79, 83, 90, 94, 98, 6, 66, 11, 15 14 18, 22, 30, 34, 41, 45, 53, 57, 68, 72, 80, 84, 91, 95, 3, 7, 87 65, 62 19, 23, 31, 35, 42, 46, 54, 58, 69, 73, 81, 85, 92, 96, 4, 8, 20, 28, 32, 36, 43, 47, 55, 59, 70, 78, 82, 86, 93, 97, 5, 9 DESCRIPTION Input/Output Pins - These are the general purpose I/O pins used by the logic array. Global Output Enable input pins. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Active Low (0) Reset pin which resets all of the registers in the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK controls become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the ISP state machine. When ispEN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the ISP state machine. When ispEN is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated input pin. SDI/IN 02 16 MODE/IN 12 37 SDO/IN 22 39 SCLK/IN 32 60 GND VCC NC1 13, 12, 1, 25, 50, 74, 89, 38, 64 2, 26, 51, 75, 99, 63, 10, 27, 52, 76, 100 88 24, 49, 61, 77, Ground (GND) VCC No Connect. 1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. Table 2-0002-2064b.eps 10 Specifications ispLSI 2064/A Pin Configuration ispLSI 2064/A 84-Pin PLCC Pinout Diagram GOE 1 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 NC1 GND I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 1NC 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O 16 I/O 12 I/O 13 I/O 14 I/O 19 I/O 20 I/O 11 GND 2 I/O 17 I/O 18 I/O 15 I/O 21 I/O 22 I/O 7 I/O 8 I/O 9 1 I/O 23 I/O 10 2MODE/IN 2SDO/IN 74 73 72 71 70 69 68 67 66 65 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 GOE 0 Y1 VCC GND Y2 NC1 SCLK/IN 32 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 Y0 VCC GND ispEN RESET 2SDI/IN ispLSI 2064/A Top View 64 63 62 61 60 59 58 57 56 55 54 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 24 0123A/2064 1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. 11 Specifications ispLSI 2064/A Pin Configuration ispLSI 2064/A 100-Pin TQFP Pinout Diagram NC1 NC1 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 NC1 GND GOE 1 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 NC1 NC1 1NC 1NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 1NC Y0 VCC GND ispEN RESET 2SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 1NC 1NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ispLSI 2064/A Top View 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC1 NC1 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 GOE 0 Y1 VCC GND Y2 NC1 SCLK/IN 32 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 NC1 NC1 1NC 1NC I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 2MODE/IN 1 GND 2SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 1NC 1NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 0766A-2064-isp 1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. 12 Specifications ispLSI 2064/A Part Number Description ispLSI XXXXX - XXX X Device Family 2064 2064A Device Number Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 80 = 81 MHz fmax X X Grade Blank = Commercial I = Industrial Package J = PLCC T = TQFP Power L = Low 0212/2064/A ispLSI 2064/A Ordering Information COMMERCIAL FAMILY fmax (MHz) 125 125 100 100 81 ispLSI 81 125 125 100 100 81 81 tpd (ns) 7.5 7.5 10 10 15 15 7.5 7.5 10 10 15 15 ORDERING NUMBER ispLSI 2064A-125LJ84 ispLSI 2064A-125LT100 ispLSI 2064A-100LJ84 ispLSI 2064A-100LT100 ispLSI 2064A-80LJ84 ispLSI 2064A-80LT100 ispLSI 2064-125LJ ispLSI 2064-125LT ispLSI 2064-100LJ ispLSI 2064-100LT ispLSI 2064-80LJ ispLSI 2064-80LT PACKAGE 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP Table 2-0041A/2064A INDUSTRIAL FAMILY fmax (MHz) 81 ispLSI 81 81 81 tpd (ns) 15 15 15 15 ORDERING NUMBER ispLSI 2064A-80LJ84I ispLSI 2064A-80LT100I ispLSI 2064-80LJI ispLSI 2064-80LTI PACKAGE 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP Table 2-0041B/2064A 13 |
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